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The branch jump instruction in risc-v requires several branch delay slots

2022-02-02 21:41:26 CSDN Q & A

RISC-V The branch jump instruction in requires several branch delay slots ?
According to the book beq Before jump, execute and,or,add Three instructions , Then the instruction of the branch target address will be executed , According to this logic, three branch delay slots are required .
But I think beq stay MEM The stage can jump to the instruction of the branch target address .
What the hell is that? 3 One is still 2 A? , Ask the great God to answer

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