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About population count in verilog

2022-08-06 16:03:12CSDN Q&A

module top_module(
input [254:0] in,
output [7:0] out );

always @(*) begin out = 0; for(int i = 0; i < 255; i++) begin if(inspan>[i]) out = out + 1; else out = out+ 0; endend

endmodule
This code has no problem on hdlbits (the one who brushed the question), but there are errors on vivado and quartus, both in the for line and the error is Error (10170): Verilog HDL syntax error at top_module.v(7) near text: "i"; expecting "=". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve thiserror. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10170): Verilog HDL syntax error at top_module.v(7) near text: "<"; expecting "<=", or "=". Check for and fix any syntax errors that appear immediately before orat the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10112): Ignored design unit "top_module" at top_module.v(1) due to previous errors

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author[CSDN Q&A],Please bring the original link to reprint, thank you.
https://en.primo.wiki/2022/218/202207302309444393.html

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